Back Annotation-Input to output Generation/IDS Architecture

Welcome to the Back Annotation – Input to Output Generation / IDS Architecture Training

This session focuses on understanding the complete back annotation flow within the IDS architecture — from reading specifications to producing fully annotated outputs in multiple formats. We will break down each stage in the pipeline, explain how data transforms along the way, and walk through a practical example.

We will cover:

  1. Specification to XRSL Generation

    • How the initial design/verification specifications are processed to create the base XRSL (eXtended Register Specification Language) file.

    • Supported specification sources (SystemRDL, IP-XACT, Word, Excel, JSON, XML, etc.) and how they are parsed into the IDS internal format.

  2. XRSL to Annotated XRSL Generation

    • How the base XRSL is enhanced with additional details from the back annotation process, producing the Annotated XRSL.

    • Enrichment with timing, physical implementation data, and other design/verification-specific metadata.

  3. Java-Based Transformation

    • How custom Java code operates on the Annotated XRSL to transform it into various deliverables.

    • Supported outputs include RTL, Verilog, SystemVerilog, UVM, C, C++, and documentation in HTML, PDF, Markdown.

  4. Practical Demonstration

    • A small example starting from a Word specification, converting it to XRSL, applying back annotation to produce the Annotated XRSL, and finally generating outputs through Java transformations.

By the end of this training, you will clearly understand how IDS back annotation works, the role of XRSL in bridging input specifications to final outputs, and how this architecture enables flexibility and automation across the design and verification process.