Welcome to IDS-NG – Design Point of View
This session focuses on using IDS-NG from a design engineer’s perspective, exploring how the tool can be leveraged to capture, manage, and optimize hardware design specifications. You will learn how IDS-NG fits into the broader design workflow, supports multiple input formats, and generates outputs essential for downstream design and verification.
We will cover:
-
Design-Oriented Specification Capture – creating and editing registers, memories, sequences, and other hardware blocks in a structured, GUI-based environment.
-
Hierarchy & Modularity – organizing specifications for complex designs, including module-level and system-level structures.
-
Parameterization & Reuse – applying design parameters and templates to enable scalable, reusable specification components.
-
Output Generation – producing RTL (Verilog/SystemVerilog), UVM testbench code, and C/C++ headers directly from the captured specifications.
-
Integration into Design Flow – aligning IDS-NG outputs with synthesis, simulation, and verification environments.
Practical Demonstration:
A step-by-step example will show how to capture a design module in IDS-NG, define its registers and interfaces, and generate synthesizable RTL along with associated verification outputs.
By the end of this training, you will understand how IDS-NG can streamline your design work, reduce manual coding errors, and ensure consistency across design and verification teams.
