Available courses
IDS-Validate is the solution for SOC/IP teams who aim to cut down the verification your validation time. The automatic generation of UVM and sequences enables exhaustive testing of memories and register maps.IDS-Validate also provides a way to generate custom tests for your boards as well as UVM and UVM-C based environments through Portable Stimulus Standard (PSS) or the GUI-based sequence template in IDS-NG. This provides a solution for your firmware engineers to write and debug their device drivers and application software.
The typical hardware/software interface involves the interaction between the central processing unit (CPU), intellectual property (IP), memory, and bus. Registers play a crucial role, with various types, addressing modes, and access attributes such as addressable/non-addressable, readable/writable, and others. The concepts of address width, register width, and data width further define the configuration.
Buses facilitate communication, with considerations for bus width, relationships between bus width and data width, bus domains, and bus families like ARM AMBA and AXI. Additional buses like Avalon, Wishbone, and I2C contribute to the diverse landscape. IPs have structured components, including register groups, internal/external registers, nested groups, memory, blocks, and subblocks.
Chips, encompassing chip size, offset, and chip-in-chip configurations, employ address concepts like register addresses, byte addressing, address units, addressing modes (compact, regalign, fullalign), and alignment principles such as offset, stride, and %=.
In the industry, IDS (IDesignSpec) is vital for efficient modeling of special registers, generating RTL and UVM models. Various methods for entering register data exist, each with its advantages. IDS outputs comprehensive documentation and verification artifacts, finding utility in diverse applications.
The SystemRDL language was specifically designed to describe and implement a wide variety of registers and memories. Using SystemRDL, developers can automatically generate and synchronize the register specification in hardware design, software development, verification, and documentation. The intent behind standardizing the language is to drastically reduce the development cycle for hardware designers, hardware verification engineers, software developers, and documentation developers.
SystemRDL is intended for
— RTL generation
— RTL verification
— SystemC generation
— Documentation — Pass through material for other tools, e.g., debuggers
— Software development
The only integrated development environment for large IP/SoC
Editor for text-based specification e.g. SystemRDL, Python, Tcl and Ace and captures registers in multiple views
GUI to support documents and spreadsheet-based specifications
Only tool for both register, sequence and checker specification
AI based sequence detection from natural language
Platform independent, available for Windows, Linux and MAC
Supports enterprise level functionality
GIT Integration - Tracking of changes and edits in IP/SOC
Cross conversion between all specification view
Concepts Covered in the Basic Technology Course:
- The basic technology course comprehensively explores fundamental concepts, including data, memory, and addressing.
- It delves into various addressing modes and methods for accessing both data and memory.
- Additionally, the course provides insights into the basics of data flow and highlights the advantages of graphical user interfaces (GUIs).
IDesignSpec GDI offer several advantages that make them a popular choice for interacting with computers and software applications:
- User-Friendly: They are designed to be intuitive and user-friendly, making them accessible to a wide range of users, including those who may not have technical expertise.
- Visual Representation: They use graphical elements like icons, buttons, menus, and windows to represent actions and data. This visual representation can make complex tasks more understandable and manageable.
- Ease of Learning: They are typically easier to learn for beginners compared to text-based interfaces or command-line interfaces (CLIs). Users can often guess the function of an icon or button based on its appearance.
Reduced Memorization: They reduce the need for users to memorize complex commands or syntax, which is often required in CLI environments. This can lead to fewer errors and less cognitive load.
Multitasking: They typically support multitasking, allowing users to have multiple applications or windows open simultaneously and switch between them easily.
Customization: It allow users to customize the interface to suit their preferences, such as rearranging toolbars or changing color schemes.
Error Handling: They can provide error messages and alerts in a user-friendly manner, helping users understand and resolve issues more easily.
The Command Line Interface (CLI) is a platform
independent text-based way of interacting with the operating system and
executing commands. While graphical user interfaces (GUIs) provide a more
intuitive and user-friendly way to interact with computers, the CLI offers
several important advantages and use cases
There are several advantages to using a
command-line interface (CLI). The most notable are:
- Speed: CLI enables you to execute commands quickly. You can combine multiple commands into a single line of text to run your program. This is much faster than navigating through menus with a GUI.
- Resources: CLI requires fewer computing resources to execute commands than a graphical interface.
- Repetitive Tasks: CLI is effective in automating repetitive tasks and can create a batch file to automate tasks at any given time.
- Power-user: A CLI is ideal for power users because it provides access to commands that are unavailable in a GUI. For example, certain tasks are system protected and cannot be accessed through a GUI.
The SystemRDL course plays a vital role in enhancing the efficiency, productivity, and reliability of digital system design. By equipping individuals with the knowledge and skills to effectively use SystemRDL, the course enables clear register specification, reusability, interoperability, verification, and documentation. It empowers designers to create robust and well-documented digital systems, ensuring successful integration and maintenance in EDA industries
IP-XACT is a standard for the description of electronic Intellectual Property (IP). It describes Extensible Markup Language (XML) documents and formats and data schemas to capture metadata that intellectual property (IP) documents use in development, implementation, and electronic systems analysis. The process is designed for use by electronic design (EDA) and electrical engineering (ESL). Developed and owned by Accellera.
IP-XACT includes XML schemas that describe different types of data and semantic systems that describe relationships between data. IDesignSpec™ can read and write different types of IP-XACT files: IDS-NG, IDS-Batch, IDS-Word, IDS-Excel.
The IP-XACT component is the central location for object metadata. Components are used to define cores, components, and buses. Translated using IDS as ipxact:material or spirit:material which includes additional properties such as top level, vendor, library names and patterns described in proper names.
- Teacher: Sakshi Saxena
Effective English communication skills are essential for professionals in a corporate environment. The primary focus of the course is to address communication within the business context. Its objective is to improve participants' proficiency in English, enabling them to communicate effectively in a range of professional scenarios, including meetings, presentations, negotiations, and written communication.
English proficiency holds significant value in corporate communication as it empowers professionals to engage in global business interactions. It facilitates efficient collaboration with international teams, ensuring clear and professional communication. Moreover, it grants access to a wealth of knowledge and resources, enabling professionals to stay updated and enhance their career prospects within the corporate world.
This training introduces IDS-Integrate, comprehensive solution for IP integration and SoC assembly. Designed to handle large-scale SoC designs, IDS-Integrate helps users assemble and package thousands of IP blocks (RTL, IP-XACT, SystemRDL, etc.) into a cohesive top-level design.
Participants will learn how to:
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Stitch IPs using interfaces, buses, or wires — manually or using intelligent automation
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Restructure, partition, or flatten SoC hierarchy
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Automate interconnect logic generation (e.g., muxes, bridges, aggregators)
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Work with SoC collateral like UPF, SDC, SV, CDC, and registers in a unified flow
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Use APIs (Python, Tcl, Java, C++) for advanced automation
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Generate custom documentation, testbenches, assertions, and models
IDS-Integrate supports both Agnisys-generated and third-party IPs, offering full flexibility through scripting and intelligent name-matching. By the end of the course, users will be able to confidently assemble complex SoCs with high accuracy, automation, and reusability.
This course trains the users on how to use IDS-Integrate for SoC Assembly and Packaging. It highlights different flows that are supported by IDS-Integrate as per the requirements of users.