IDS-Validate is the solution for SOC/IP teams who aim to cut down the verification your validation time. The automatic generation of UVM and sequences enables exhaustive testing of memories and register maps.IDS-Validate also provides a way to generate custom tests for your boards as well as UVM and UVM-C based environments through Portable Stimulus Standard (PSS) or the GUI-based sequence template in IDS-NG. This provides a solution for your firmware engineers to write and debug their device drivers and application software.
The typical hardware/software interface involves the interaction between the central processing unit (CPU), intellectual property (IP), memory, and bus. Registers play a crucial role, with various types, addressing modes, and access attributes such as addressable/non-addressable, readable/writable, and others. The concepts of address width, register width, and data width further define the configuration.
Buses facilitate communication, with considerations for bus width, relationships between bus width and data width, bus domains, and bus families like ARM AMBA and AXI. Additional buses like Avalon, Wishbone, and I2C contribute to the diverse landscape. IPs have structured components, including register groups, internal/external registers, nested groups, memory, blocks, and subblocks.
Chips, encompassing chip size, offset, and chip-in-chip configurations, employ address concepts like register addresses, byte addressing, address units, addressing modes (compact, regalign, fullalign), and alignment principles such as offset, stride, and %=.
In the industry, IDS (IDesignSpec) is vital for efficient modeling of special registers, generating RTL and UVM models. Various methods for entering register data exist, each with its advantages. IDS outputs comprehensive documentation and verification artifacts, finding utility in diverse applications.
The SystemRDL language was specifically designed to describe and implement a wide variety of registers and memories. Using SystemRDL, developers can automatically generate and synchronize the register specification in hardware design, software development, verification, and documentation. The intent behind standardizing the language is to drastically reduce the development cycle for hardware designers, hardware verification engineers, software developers, and documentation developers.
SystemRDL is intended for
— RTL generation
— RTL verification
— SystemC generation
— Documentation — Pass through material for other tools, e.g., debuggers
— Software development
The only integrated development environment for large IP/SoC
Editor for text-based specification e.g. SystemRDL, Python, Tcl and Ace and captures registers in multiple views
GUI to support documents and spreadsheet-based specifications
Only tool for both register, sequence and checker specification
AI based sequence detection from natural language
Platform independent, available for Windows, Linux and MAC
Supports enterprise level functionality
GIT Integration - Tracking of changes and edits in IP/SOC
Cross conversion between all specification view
Concepts Covered in the Basic Technology Course:
IDesignSpec GDI offer several advantages that make them a popular choice for interacting with computers and software applications:
Reduced Memorization: They reduce the need for users to memorize complex commands or syntax, which is often required in CLI environments. This can lead to fewer errors and less cognitive load.
Multitasking: They typically support multitasking, allowing users to have multiple applications or windows open simultaneously and switch between them easily.
Customization: It allow users to customize the interface to suit their preferences, such as rearranging toolbars or changing color schemes.
Error Handling: They can provide error messages and alerts in a user-friendly manner, helping users understand and resolve issues more easily.
The Command Line Interface (CLI) is a platform
independent text-based way of interacting with the operating system and
executing commands. While graphical user interfaces (GUIs) provide a more
intuitive and user-friendly way to interact with computers, the CLI offers
several important advantages and use cases
There are several advantages to using a
command-line interface (CLI). The most notable are:
IP-XACT is a standard for the description of electronic Intellectual Property (IP). It describes Extensible Markup Language (XML) documents and formats and data schemas to capture metadata that intellectual property (IP) documents use in development, implementation, and electronic systems analysis. The process is designed for use by electronic design (EDA) and electrical engineering (ESL). Developed and owned by Accellera.
IP-XACT includes XML schemas that describe different types of data and semantic systems that describe relationships between data. IDesignSpec™ can read and write different types of IP-XACT files: IDS-NG, IDS-Batch, IDS-Word, IDS-Excel.
The IP-XACT component is the central location for object metadata. Components are used to define cores, components, and buses. Translated using IDS as ipxact:material or spirit:material which includes additional properties such as top level, vendor, library names and patterns described in proper names.
Effective English communication skills are essential for professionals in a corporate environment. The primary focus of the course is to address communication within the business context. Its objective is to improve participants' proficiency in English, enabling them to communicate effectively in a range of professional scenarios, including meetings, presentations, negotiations, and written communication.
English proficiency holds significant value in corporate communication as it empowers professionals to engage in global business interactions. It facilitates efficient collaboration with international teams, ensuring clear and professional communication. Moreover, it grants access to a wealth of knowledge and resources, enabling professionals to stay updated and enhance their career prospects within the corporate world.
This training provides a practical understanding of the IP-XACT (IEEE 1685) standard used for IP and SoC integration. It covers key constructs, design environment setup, and tool-based implementation. Participants will learn how to describe, configure, and integrate IPs efficiently using IP-XACT, along with advanced concepts like memory maps, bus interfaces, TGI APIs, and vendor extensions.
Through interactive sessions and lab exercises, attendees will gain hands-on experience in using IP-XACT as both input and output in design and verification flows, understand its interoperability with SystemRDL, and explore its support within IDS tools.
Outcome:
By the end of the training, participants will be able to effectively apply IP-XACT to standardize IP data, automate integration, and streamline SoC design and verification.
This training introduces IDS-Integrate, comprehensive solution for IP integration and SoC assembly. Designed to handle large-scale SoC designs, IDS-Integrate helps users assemble and package thousands of IP blocks (RTL, IP-XACT, SystemRDL, etc.) into a cohesive top-level design.
Participants will learn how to:
Stitch IPs using interfaces, buses, or wires — manually or using intelligent automation
Restructure, partition, or flatten SoC hierarchy
Automate interconnect logic generation (e.g., muxes, bridges, aggregators)
Work with SoC collateral like UPF, SDC, SV, CDC, and registers in a unified flow
Use APIs (Python, Tcl, Java, C++) for advanced automation
Generate custom documentation, testbenches, assertions, and models
IDS-Integrate supports both Agnisys-generated and third-party IPs, offering full flexibility through scripting and intelligent name-matching. By the end of the course, users will be able to confidently assemble complex SoCs with high accuracy, automation, and reusability.
This training introduces IDesignSpec (IDS), a powerful and flexible solution for creating, managing, and generating register specifications across multiple input formats like Excel, Word, and SystemRDL. IDS enables seamless generation of RTL, UVM, IP-XACT, documentation, and more—suitable for IP and SoC-level design flows.
Participants will learn how to:
Use IDS-NG, Excel/Word Add-ins, and IDS-Batch in both GUI and CLI modes
Create register specifications using Excel, Word, or SystemRDL
Define register access policies, fields, and special attributes like shadow, alias, lock, counters, and interrupts
Automatically generate synthesizable RTL for various bus protocols
Integrate 3rd-party IPs using references and variants
Parameterize register and field definitions for reuse and scalability
Incorporate low-power design elements
Handle complex designs involving clock domain crossing (CDC) and multiple bus domains
Generate UVM models, IP-XACT views, and documentation from a single source
Ensure traceability and support functional safety requirements
Automate the design flow using Tcl, or Velocity template
The training includes hands-on demos for RTL, UVM, IP-XACT, and documentation generation. By the end of the course, users will be able to build consistent, scalable, and traceable register designs with a high degree of automation and flexibility.
The SystemRDL course plays a vital role in enhancing the efficiency, productivity, and reliability of digital system design. By equipping individuals with the knowledge and skills to effectively use SystemRDL, the course enables clear register specification, reusability, interoperability, verification, and documentation. It empowers designers to create robust and well-documented digital systems, ensuring successful integration and maintenance in EDA industries
XSLT Training – XRSL Transformations
This session covers the basics of the XSLT language and its role in Agnisys workflows, focusing on how XRSL specifications are transformed into various output formats (register maps, documentation, code) using XSLT templates. Includes simple examples of transformations to illustrate the process.
SystemVerilog Assertions (SVA) – Training Overview
This session introduces the fundamentals of SystemVerilog Assertions, focusing on:
Concurrent Assertions for temporal checks over time
Sequential Expressions to describe ordered events
Common SVA Operators (##, [*], |->, |=>, etc.) and their usage
The training includes examples within a verification environment to validate protocol compliance, timing checks, and functional requirements.
Directory Structure Setup (as part of Verification Environment Training)
This section covers how to set up and maintain the verification environment’s directory structure using Git. It explains:
Cloning the verification repository
Organizing files for AMBA-based Mentor VIP testbenches
Ensuring consistent structure for sequences, makefiles, and waveform outputs
Proper setup ensures smooth integration, compilation, and debugging in the verification flow.
Welcome to GitHub Training
This session will cover the core version control operations used in our workflows. You will learn how to:
Create and switch branches for feature development
Commit changes and maintain clear commit messages
Push and pull code between local and remote repositories
Merge branches while resolving conflicts effectively
By the end, you’ll be able to manage your code collaboratively using GitHub with confidence.
Welcome to Functional Safety – Part 2
In this session, we will build on the concepts from Part 1 and focus on industry standards and software-level safety. We will explore the ISO 26262 standard, its relevance to our workflows, and key safety management concepts.
Topics include:
ISO 26262 Standard – scope, requirements, and impact on development
Safety Management – planning, monitoring, and reporting for safety goals
Product Development at the Software Level – applying safety principles in code
Qualification Flow for Software Tools – ensuring tool reliability
Methods for Determining Tool Confidence Level (TCL) – risk assessment and mitigation
By the end of this session, you will understand how functional safety principles translate into software processes and tool qualification to meet compliance requirements.
Welcome to Functional Safety – Part 1
This session provides an overview of Functional Safety Mechanisms and the processes we follow to ensure safety compliance in our designs. We will cover the objectives and need for FSMs, how traceability is maintained, and the complete workflow from development to validation.
We will discuss:
FSM Objectives & Need – why safety mechanisms are essential
Traceability – linking requirements to design and verification evidence
Training & Development Process – skill-building and implementation practices
Testing Process – simulations, fault injections, and regression checks
Validation Kit – ensuring FSM performance in real-world scenarios
Compliance Management – meeting safety standards and audit readiness
Change Management – handling updates without breaking safety guarantees
By the end of this session, you will understand the foundational elements of FSMs and how they fit into our functional safety workflow.
Welcome to the Syappa Training
This session introduces Syappa, our in-house script for generating random XRSL testcases. You will learn how to control parameters such as the number of registers, blocks, and applied properties, enabling quick creation of diverse test inputs. We will also cover how these generated cases are used for tool validation, regression runs, and edge-case testing.
Welcome to the Functional Safety Mechanism (FSM) Training
This session explains our company’s end-to-end process for developing and releasing Functional Safety Mechanisms. You will learn how an FSM request moves from ticket creation in FogBugz, through implementation, testing, and regression, to documentation, Excel sheet updates, and final release.
We will cover:
Raising and tracking tickets
Implementing changes per safety and coding standards
Running simulations and regression tests
Updating documentation and required Excel trackers (Feature trace, Dashboard, Release Checklist)
Completing peer review and release steps
By the end, you will know how to follow our FSM workflow to deliver safe, compliant, and properly documented releases.
Welcome to the Diff Classifier Training
This session introduces the Diff Classifier — a custom script developed to compare golden outputs with newly generated outputs during regression testing. The goal is to quickly identify, classify, and prioritize differences so that verification teams can focus on meaningful changes rather than sifting through large output files manually.
We will cover:
Purpose of the Diff Classifier – streamlining regression analysis by automating file comparisons.
How It Works – parsing both golden and generated outputs, detecting differences, and categorizing them as expected, unexpected, or ignorable.
Integration in Regression Flow – where and how the script fits into the IDS testing pipeline.
Output Reports – understanding the diff summary, highlighted changes, and classification tags.
Benefits – faster debugging, reduced manual review time, and improved regression efficiency.
Practical Demonstration:
We will run the Diff Classifier on sample golden and generated outputs, review the categorized differences, and show how this helps in making pass/fail decisions more quickly.
By the end of this session, you will know how to run the Diff Classifier, interpret its results, and integrate it into your daily regression workflow to speed up verification signoff.
Welcome to the Overview of Special Registers Training
This session provides an in-depth understanding of various special register types used in hardware design and verification. These registers go beyond simple read/write functionality, enabling advanced control, monitoring, and optimization within a system-on-chip (SoC) or IP block.
We will cover:
Alias Registers – multiple register addresses referring to the same physical storage.
Counter Registers – automatically incrementing or decrementing registers for event or time tracking.
Interrupt Registers – controlling and monitoring hardware interrupts.
Paged Registers – implementing memory-efficient paging for large register sets.
Lock Registers – controlling access to critical configuration fields.
FIFO Registers – enabling first-in-first-out data storage and retrieval.
Trigger & Buffer Registers – initiating hardware actions or temporarily storing streaming data.
TMR (Triple Modular Redundancy) Registers – improving reliability through redundant storage and voting mechanisms.
RWPair Registers – paired read/write registers for specific control/status use cases.
Practical Demonstration:
We will examine small examples of each register type within IDS-NG, showing how to define them, configure their behavior, and generate outputs for RTL and verification environments.
By the end of this training, you will understand when and why to use each special register type, and how to implement them effectively in your projects.
Welcome to Simulation Training – AMBA Buses with Questa SIM VIP
This training is designed to equip you with the skills to simulate and verify various AMBA bus protocols using Questa SIM VIP in our server-based environment. You will learn how to set up, configure, and run simulations for different AMBA interfaces, leveraging the pre-installed VIP (Verification IP) infrastructure we have prepared.
We will cover:
Overview of AMBA Protocols – including AHB, AXI, APB, and others, with a focus on their roles in SoC design.
Introduction to Questa SIM VIP – features, capabilities, and how it integrates with your verification environment.
Server Setup & Access – how to connect to our simulation servers and use the configured environment.
Testbench Integration – connecting AMBA VIPs to DUTs, configuring parameters, and setting up monitors and checkers.
Running & Debugging Simulations – compiling, executing, and analyzing simulation results.
Practical Demonstration:
We will run a sample simulation for one AMBA protocol (e.g., AXI) using the Questa SIM VIP setup on our server, showcasing the process from environment setup to result analysis.
By the end of this training, you will be able to confidently use our server-based Questa SIM VIP setup to simulate and verify AMBA bus protocols for your projects.
Welcome to IDS-NG – Design Point of View
This session focuses on using IDS-NG from a design engineer’s perspective, exploring how the tool can be leveraged to capture, manage, and optimize hardware design specifications. You will learn how IDS-NG fits into the broader design workflow, supports multiple input formats, and generates outputs essential for downstream design and verification.
We will cover:
Design-Oriented Specification Capture – creating and editing registers, memories, sequences, and other hardware blocks in a structured, GUI-based environment.
Hierarchy & Modularity – organizing specifications for complex designs, including module-level and system-level structures.
Parameterization & Reuse – applying design parameters and templates to enable scalable, reusable specification components.
Output Generation – producing RTL (Verilog/SystemVerilog), UVM testbench code, and C/C++ headers directly from the captured specifications.
Integration into Design Flow – aligning IDS-NG outputs with synthesis, simulation, and verification environments.
Practical Demonstration:
A step-by-step example will show how to capture a design module in IDS-NG, define its registers and interfaces, and generate synthesizable RTL along with associated verification outputs.
By the end of this training, you will understand how IDS-NG can streamline your design work, reduce manual coding errors, and ensure consistency across design and verification teams.
Welcome to the Overview of Third-Party Tools for Compilation, Synthesis, and Verification
This session introduces the key third-party tools we use in our development and verification workflow. You will learn what each tool does, when to use it, and how it integrates into our overall flow for compiling code, synthesizing designs, and running simulations.
We will cover:
Compilation Tools – e.g., GCC for compiling C/C++ programs
Verification Tools – Questa SIM, VCS, IRUN, vsim for simulation and functional verification
Synthesis Tools – overview of how synthesis is performed using industry-standard EDA tools
Usage & Integration – basic command-line operations, licensing, and how these tools fit into our build and regression process
By the end, you will have a clear understanding of the role each tool plays and how to use them effectively in your daily work.
Welcome to the IDSWord, IDSExcel / IDSBatch, and IDS-NG Training
This session introduces you to the primary input creation tools within the Agnisys ecosystem — IDSWord, IDSExcel / IDSBatch, and IDS-NG. You will learn how each tool is used to capture register specifications, how they integrate into the IDS flow, and when to choose one over the other for your projects.
We will cover:
IDSWord – capturing register specifications directly within Microsoft Word using our embedded templates and macros.
IDSExcel / IDSBatch – entering register definitions in Excel or batch mode for quick, large-scale specification handling.
IDS-NG – using the graphical user interface to create and edit register specifications interactively.
Practical Demonstration:
A small example will show how to capture a register specification in the IDS-NG GUI — from adding fields, setting attributes, and defining bit positions to saving and generating the corresponding IDS input files.
By the end of this session, you will understand the strengths of each tool, be able to select the most efficient input method for your needs, and confidently capture accurate register specifications for IDS processing.
Welcome to the FogBugz Training – Ticket Handling, Tracking, and Agnisys Norms
This training will guide you through the complete process of using FogBugz for efficient ticket management and issue tracking at Agnisys. You will learn not only the technical steps for creating, updating, and closing tickets but also the internal norms and best practices we follow to ensure smooth collaboration and clear communication across teams.
We will cover:
Ticket Lifecycle – from creation to closure, including prioritization, categorization, and status updates.
Tracking and Reporting – monitoring progress, linking related cases, and using search filters effectively.
Agnisys-Specific Norms – naming conventions, expected response times, escalation procedures, and documentation standards.
Collaboration in FogBugz – adding comments, attachments, and maintaining clear audit trails for project history.
By the end of this training, you will be able to confidently manage tickets in FogBugz while following Agnisys guidelines, ensuring tasks are well-tracked, transparent, and resolved efficiently.
Welcome to the Importance of Regression in Agnisys – Scripts and General Scripts for Daily Use Training
This session highlights why regression testing is critical in Agnisys for ensuring product stability, catching unintended changes, and maintaining quality across releases. You will learn how regression fits into our development workflow and how to use our in-house automation scripts for efficient daily work.
We will cover:
Role of Regression – verifying that new changes do not break existing functionality
Agnisys Regression Flow – how code changes move from implementation to regression execution and analysis
Regression Scripts – running, monitoring, and reporting results
General Daily Use Scripts – quick utilities for comparisons, log parsing, output validation, and other routine tasks
Best Practices – organizing test runs, handling failures, and updating golden outputs when required
By the end, you will understand how to run regressions effectively and use our scripts to save time, reduce manual errors, and improve development productivity.
Welcome to the Back Annotation – Input to Output Generation / IDS Architecture Training
This session focuses on understanding the complete back annotation flow within the IDS architecture — from reading specifications to producing fully annotated outputs in multiple formats. We will break down each stage in the pipeline, explain how data transforms along the way, and walk through a practical example.
We will cover:
Specification to XRSL Generation
How the initial design/verification specifications are processed to create the base XRSL (eXtended Register Specification Language) file.
Supported specification sources (SystemRDL, IP-XACT, Word, Excel, JSON, XML, etc.) and how they are parsed into the IDS internal format.
XRSL to Annotated XRSL Generation
How the base XRSL is enhanced with additional details from the back annotation process, producing the Annotated XRSL.
Enrichment with timing, physical implementation data, and other design/verification-specific metadata.
Java-Based Transformation
How custom Java code operates on the Annotated XRSL to transform it into various deliverables.
Supported outputs include RTL, Verilog, SystemVerilog, UVM, C, C++, and documentation in HTML, PDF, Markdown.
Practical Demonstration
A small example starting from a Word specification, converting it to XRSL, applying back annotation to produce the Annotated XRSL, and finally generating outputs through Java transformations.
By the end of this training, you will clearly understand how IDS back annotation works, the role of XRSL in bridging input specifications to final outputs, and how this architecture enables flexibility and automation across the design and verification process.
Welcome to the High-Level Overview of Agnisys Tools
This course provides a comprehensive look at the Agnisys Design System (IDS) and its ecosystem of tools. You will gain a clear understanding of the complete workflow — from the formats and sources that serve as inputs, to the various design and verification outputs, and the automatically generated documentation that supports your work.
We will cover:
All Inputs to IDS – supported formats including SystemRDL, IP-XACT, Word, Excel, IDS-NG, JSON, XML, and more.
Outputs – the range of design, verification, and deliverable files generated by IDS such as RTL, Verilog, SystemVerilog, UVM, C, and C++.
Documentation Outputs – auto-generated project documentation in HTML, PDF, and Markdown formats.
By the end of this session, you will have a high-level understanding of how different inputs are processed, how outputs are produced, and how to leverage IDS for faster and more accurate design and documentation.
Welcome to the IT Onboarding & Tools Familiarization Course
This course is designed to provide you with a complete introduction to the essential IT systems, tools, and resources used within our company. Whether you are a new joiner or looking for a quick refresher, this program will guide you step-by-step through setting up and accessing all critical platforms needed for your work.
We will cover:
Login setup for Gmail, your company email, and other key accounts.
Access and usage of our website ticketing systems — Bugzilla and FogBugz — for reporting and tracking tasks or issues.
Server logins and basic server access guidelines.
Internal Wiki and Google Drive for knowledge sharing and file management.
Installation of essential tools required for your role.
OpenVPN setup for secure remote access to company resources.
Slack setup for team communication and collaboration.
By the end of this course, you will be equipped to efficiently access, navigate, and utilize all our core IT tools, ensuring you can work productively from day one.
Welcome to the Company Induction Program
The Induction Program is your first step into understanding who we are, what we stand for, and how we work together as a team. This course will give you a complete overview of our organization, its people, and its culture, so you can feel connected and confident from your very first day.
We will explore:
Company Overview – our history, mission, vision, and key achievements.
In the News – recent milestones, recognitions, and media highlights.
Our Team – meet the people who make things happen, from leadership to your immediate colleagues.
Policy Overview – key guidelines, workplace policies, and best practices.
Our Culture – the values, work ethics, and collaborative spirit that define us.
By the end of this session, you will have a strong understanding of our company’s identity, your place within it, and how we can work together towards our shared goals.
