Available courses
This training introduces IDS-Integrate, comprehensive solution for IP integration and SoC assembly. Designed to handle large-scale SoC designs, IDS-Integrate helps users assemble and package thousands of IP blocks (RTL, IP-XACT, SystemRDL, etc.) into a cohesive top-level design.
Participants will learn how to:
Stitch IPs using interfaces, buses, or wires — manually or using intelligent automation
Restructure, partition, or flatten SoC hierarchy
Automate interconnect logic generation (e.g., muxes, bridges, aggregators)
Work with SoC collateral like UPF, SDC, SV, CDC, and registers in a unified flow
Use APIs (Python, Tcl, Java, C++) for advanced automation
Generate custom documentation, testbenches, assertions, and models
IDS-Integrate supports both Agnisys-generated and third-party IPs, offering full flexibility through scripting and intelligent name-matching. By the end of the course, users will be able to confidently assemble complex SoCs with high accuracy, automation, and reusability.
This training introduces IDesignSpec (IDS), a powerful and flexible solution for creating, managing, and generating register specifications across multiple input formats like Excel, Word, and SystemRDL. IDS enables seamless generation of RTL, UVM, IP-XACT, documentation, and more—suitable for IP and SoC-level design flows.
Participants will learn how to:
Use IDS-NG, Excel/Word Add-ins, and IDS-Batch in both GUI and CLI modes
Create register specifications using Excel, Word, or SystemRDL
Define register access policies, fields, and special attributes like shadow, alias, lock, counters, and interrupts
Automatically generate synthesizable RTL for various bus protocols
Integrate 3rd-party IPs using references and variants
Parameterize register and field definitions for reuse and scalability
Incorporate low-power design elements
Handle complex designs involving clock domain crossing (CDC) and multiple bus domains
Generate UVM models, IP-XACT views, and documentation from a single source
Ensure traceability and support functional safety requirements
Automate the design flow using Tcl, or Velocity template
The training includes hands-on demos for RTL, UVM, IP-XACT, and documentation generation. By the end of the course, users will be able to build consistent, scalable, and traceable register designs with a high degree of automation and flexibility.
This training introduces IDesignSpec (IDS), a powerful and flexible solution for creating, managing, and generating register specifications across multiple input formats like Excel, Word, and SystemRDL. IDS enables seamless generation of RTL, UVM, IP-XACT, documentation, and more—suitable for IP and SoC-level design flows.
Participants will learn how to:
-
Use IDS-NG, Excel/Word Add-ins, and IDS-Batch in both GUI and CLI modes
-
Create register specifications using Excel, Word, or SystemRDL
-
Define register access policies, fields, and special attributes like shadow, alias, lock, counters, and interrupts
-
Automatically generate synthesizable RTL for various bus protocols
-
Integrate 3rd-party IPs using references and variants
-
Parameterize register and field definitions for reuse and scalability
-
Incorporate low-power design elements
-
Handle complex designs involving clock domain crossing (CDC) and multiple bus domains
-
Generate UVM models, IP-XACT views, and documentation from a single source
-
Ensure traceability and support functional safety requirements
-
Automate the design flow using Tcl, or Velocity template
The training includes hands-on demos for RTL, UVM, IP-XACT, and documentation generation. By the end of the course, users will be able to build consistent, scalable, and traceable register designs with a high degree of automation and flexibility.
This training introduces IDS-Integrate, comprehensive solution for IP integration and SoC assembly. Designed to handle large-scale SoC designs, IDS-Integrate helps users assemble and package thousands of IP blocks (RTL, IP-XACT, SystemRDL, etc.) into a cohesive top-level design.
Participants will learn how to:
-
Stitch IPs using interfaces, buses, or wires — manually or using intelligent automation
-
Restructure, partition, or flatten SoC hierarchy
-
Automate interconnect logic generation (e.g., muxes, bridges, aggregators)
-
Work with SoC collateral like UPF, SDC, SV, CDC, and registers in a unified flow
-
Use APIs (Python, Tcl, Java, C++) for advanced automation
-
Generate custom documentation, testbenches, assertions, and models
IDS-Integrate supports both Agnisys-generated and third-party IPs, offering full flexibility through scripting and intelligent name-matching. By the end of the course, users will be able to confidently assemble complex SoCs with high accuracy, automation, and reusability.
Updates for the last year using Spreadsheet view
